Universal serial bus flash memory integrated circuit device

ABSTRACT

The invention provides a flash memory integrated circuit device that is connectable to a computer via a universal serial bus. The universal serial bus (USB) has become a standard serial interface, which allows data to be stored in and read from an external memory device at high speed. Therefore, it is advantageous to combine the benefits of a flash memory device with the speed of the universal serial bus. In addition, by designing the flash memory device with a USB interface, the flash memory device appears as a standard USB storage device, which permits the host and flash memory device to connect and interact with ease.

BACKGROUND OF THE INVENTION

[0001] 1. Field of Invention

[0002] The present invention relates to a flash memory device, and moreparticularly, to a universal serial bus flash memory integrated circuitthat is connectable via a universal serial bus.

[0003] 2. Description of Related Art

[0004] Flash memory has become an important means for storing data forthe advantage of high mobility and non-erasable. This is an extremelyuseful way of storing data for portable devices such as handhelddevices. The convenience that flash memory provides gives it numerousadvantages over traditional mass storage devices such as hard disks.Besides portability, flash memory further offers advantages such as lowpower consumption, reliability, small size and high speed.

[0005] Flash memory is non-volatile which means that it retains itsstored data even after power is turned off. This is an improvement overstandard random access memory (RAM), which is volatile and thereforelooses stored data when power is turned off.

[0006] Universal serial transmission interface is the standard ofPC/NB/IA products. PC/NB/IA products are bootable by storage medium ofserial transmission interface, thereby increasing the possibility ofsubstituting serial transmission interface storage medium for harddiskdrive. Due to external attachment arrangement, existing serialtransmission interface storage media cause certain inconveniences.

[0007] In order to fit different function requirements, currentsmall-sized IA products, such as PDA, industrial computer, digitalcamera, and the like are commonly provided with an operation system, forexample, Win CE/Linux. The hardware architecture requires a CPU and aNOR type flash memory for storing program code. If it is necessary tostore data, SRAM or built-in NAND flash memory, or external memory cardis needed. The aforesaid three measures are not of standard interface toWin CE/Linux. The designer needs to modify the driving program orapplication program of these operation systems. Therefore, it requiresmuch effort and money on these interfaces when developing a new product.

[0008] As the number of mobile, portable, or handheld devices grows, thepopularity of flash memory increases. The most common type of flashmemory is in the form of a removable memory card. This card allows thecontents of the flash memory to be transferred easily between devices orcomputers.

[0009] However, when moving the flash memory card between devices, anadditional host or adapter is required in order for the host tocommunicate with the flash card. Many devices may not have the built-inability to connect to a flash card, therefore a special adapter or cardmust be installed in the host device. In addition, the bus architecturecan limit the speed of data transfer between the host and flash memorydevice.

[0010] Therefore, there is a need for a flash memory device that can bedirectly connected to a host device without the need for special cablesor adapters.

SUMMARY OF THE INVENTION

[0011] To achieve these and other advantages and in order to overcomethe disadvantages of a conventional flash memory card in accordance withthe purpose of the invention as embodied and broadly described herein,the present invention provides a flash memory integrated circuit devicethat is connectable to a host via a universal serial bus.

[0012] The universal serial bus (USB) has become a standard serialinterface, which allows data to be stored in and read from an externalmemory device at high speed. Therefore, it is advantageous to combinethe benefits of a flash memory device with the speed of the universalserial bus. In addition, by designing the flash memory device with a USBinterface, the flash memory device appears as a standard USB storagedevice, which permits the host and flash memory device to connect andinteract with ease.

[0013] The main board of the flash memory integrated circuit devicecomprises a controller and at least one flash memory chip. A USBconnector connects the flash memory integrated circuit device with a USBhost. The flash memory on the main board comprises at least one flashmemory chip but as described below, the memory capacity of the flashmemory device can be easily expanded.

[0014] In an embodiment of the present invention, the memory storagedevice further comprises an extension stack connector that allows forextending the number of flash memories on slave boards. The extensionstack connector connects the pins needed by the flash memory chip on theslave board with the controller on the main board. In this way, thememory capacity of the flash memory device can be conveniently expandedas required.

[0015] The controller is a major component of the device. The controllercontrols commands and data between the USB host and manages data in theflash memory array or module. It is preferred that the controller is ofa single chip design that does not need external ROM or RAM.

[0016] A regulator regulates the voltage for the memory storage device.Typically, flash memory requires 3.3 volts or 5.0 volts. Some flashmemory devices utilize means of switching between 3.3 volts and 5.0volts as required by the flash memory. However, an advantage of theflash memory device of the present invention is that the flash memorydevice only needs 3.3 volts. Therefore, regardless if 5.0 volts or 3.3volts is received from the host, the regulator will ensure that 3.3volts is available for the USB transceiver without the need fordetecting and converting the voltage.

[0017] A clock generator, for example a crystal, generates a clocksignal for the controller of the flash memory device.

[0018] The flash memory integrated circuit device of an embodiment ofthe present invention further comprises an indicator, for example an LEDindicator, which indicates the status of the memory storage device suchas whether it is busy or in standby.

[0019] The main board of the flash memory device can also have a stackconnector for connecting a slave board to the main board for extendingthe memory size with flash memory arrays. The slave board comprises atleast one additional flash memory module or array. Multiple slave boardscan be connected in order to provide unlimited memory expansion.

[0020] A write protection switch provides write protection from the USBhost. The switch has at least two positions; a position for allowing thehost to read and write normally, and another position for writeprotection. When the switch is in the write protect position, the hostcan read data but cannot write or erase data.

[0021] The controller of the flash memory device of the presentinvention performs numerous functions. Among these functions iscontrolling the USB interface. The controller follows the USBspecification for physical and logical protocol. The controller furthercomprises a FIFO controller buffer. The controller receives command andparameter packets from the USB host, which are then stored in a specialregister defined by the controller. The controller is also responsiblefor controlling the transfer of data to and from the USB host. Inaddition, the controller also provides status data to the USB host.

[0022] When the host sends a write command, an interrupt is generatedand sent to the controller microprocessor to inform the microprocessorof the command and the command location. The microprocessor, for examplean 8 or 16-bit microprocessor, is a major component of the controller.The microprocessor reads the USB commands and parameters from theregister. The microprocessor also executes the commands with parameters.The microprocessor manages and maps the USB FIFO address to thecontroller buffer while receiving or transferring data to and from theUSB host. Also, the microprocessor manages commands such as erase,program, or read for the flash memory array. In addition, themicroprocessor executes the addressing method according to the algorithmof the controller.

[0023] Microprocessor ROM stores the program code of the controller andis built into the controller. Microprocessor RAM is a system RAM used bythe controller when executing USB commands or the flash algorithm. Byeliminating the requirement for off-chip memory, the system cost isreduced.

[0024] A system buffer is used as a cache, which is provided forbuffering between the USB interface and the flash memory arrayinterface. It is also the FIFO of the USB protocol and the direction mapto the buffer. The microprocessor manages the addresses of this buffer.As required, the buffer can be accessed by byte or word.

[0025] The flash memory integrated circuit device of the presentinvention further comprises a hardware state machine for creating theread and write timing to the system buffer between the USB host and theflash memory. A flash interface and circuit, controls the read and writecommands to the flash memory array. In an embodiment of the presentinvention this is a pure hardware circuit.

[0026] In addition, an ECC circuit encodes the ECC code while data iswriting to the flash memory array from the buffer cache and decodes theECC code while data is read from the flash memory array to the buffercache. If an ECC error occurs, the ECC circuit will determine the wordor byte address in the buffer cache and correct the error.

[0027] The USB command implementation comprises the controller receivingcommands and parameters from the USB host and storing them in a registerdefined by the controller. An interrupt is generated and sent to informthe microprocessor that a command has been received.

[0028] The controller receives and transfers data to and from the USBhost according to the USB logical and physical specification. Theaddressing method comprises managing the flash memory erase, read, andwrite commands and manages the physical to logical mapping.

[0029] When the USB Host writes a command and parameter to the memorystorage device, the controller will store it in a specified register.The data will then be read by the microprocessor as information from theUSB host. According to the standard USB specification, the requestparameter comprises 7 bits as shown in FIG. 5. Bits D6-D5 of thebmRequest Type designate the type of command protocol. The types includestandard, class, and vendor. The flash memory device of the presentinvention supports all three of these types of protocols. The standardtype is the standard device request, which is a common command such asUSB_Get_Status or USB_set_Feature.

[0030] An embodiment of the flash memory integrated circuit device ofthe present invention utilizes the USB mass storage class with thebulk/control/interrupt transport.

[0031] Due to the physical limit of the flash memory, before the writecommand can be performed, an erase command must be executed first.Typical flash memory can function normally only until being erased aboutone million times, so minimizing the erase steps to maximize the flashmemory's usage life is very important. Therefore, the present inventionprovides a link table and a mother/child framework to achieve this aim.

[0032] Following is a description of the use of the link table. Wheninitializing flash, all blocks are searched and a record of therelationship between the physical and logical block that the search hasfound, becomes the link table. At the same time, the unused physicalblocks are put into the spare region for the FIFO queue to use. Next,the logical block in the Link Table is used to find the correspondingphysical block address. By doing so, data associated with a particularphysical block can accurately be written or retrieved.

[0033] When writing data to the flash memory, an erased block (newblock) may need to be taken to replace an old block. Then data iswritten into the new block. Finally, the data, which has been notchanged, is moved from the old block to the new block. This completesthe action of writing a page's data.

[0034] If multiple pages of data are to be written, the above steps arerepeated. However, if data is repeatedly written into the same block,many unnecessary erase and move actions are performed. This not onlywastes time but also reduces the lifetime of the flash. Therefore, inthe flash memory device of the present invention, the erase action isavoided when repeatedly writing data to the same block and the moveaction is performed only when changing blocks. By using this method, notonly is the lifetime of the flash increased but the efficiency of thedevice is also increased.

[0035] Following is a write data example. 32 sectors of data are to bewritten to flash which starts at block/page 0/0. The total physicalblock/logical block is 1024/992. The total spare blocks for the FIFO is32. No blocks are defective. There are 32 pages per block. Child blocknumber 03E0h, which is pointed to by the head pointer is taken from theFIFO spare region. The head pointer is then incremented and 32 pages ofdata are programmed into the child block. Child block number 03E0h isfilled into the mother block's logical block address 0000h in the linktable. Mother block 0000h is erased and the tail pointer is incremented.Then, mother block number 0000h is filled into the tail pointer pointaddress in the spare region.

[0036] Following is a description of a write procedure according to anembodiment of the present invention.

[0037] The host writes the corresponding write command and the addressparameter to the memory storage device which then begins execution ofthe program flash algorithm. Then, the logical address from the USB hostis converted to the flash memory physical block and page address. Thecontroller checks to see if a child block exists.

[0038] If a child block doesn't exist, a clean block is taken from theFIFO queue to create a child block for the current write command. Then,the current flash memory logical page number is checked to see if whatis to be written is equal to “0” or not. If equal to “0”, the data fromthe host to the flash memory is programmed into the buffer and thesector count number is decremented. This process is repeated until thesector count number is equal to “0”. If what is to be written is notequal to “0”, the data from the mother block (which is clean) is movedto the child block between the sections “last page written” and the“current write page”. Then, the data from the host to the flash memoryis programmed into the buffer and the sector count number isdecremented. This process is repeated until the sector count number isequal to “0”.

[0039] If a child block exists, the current flash memory's logical blockis checked to see if what is to be written is equal to the last flashmemory logical block that was written. If it is not equal, the data fromthe mother block is moved to the child block between the sections “lastpage written” and the “end page of this block”. Then, the mother blockis erased. The link table in the controller is updated substituting theoriginal mother block address with the child block address. Then, theerased mother block is put back into the FIFO queue as a clean block. Ifwhat is to be written is equal to the last flash memory logical blockthat was written, the current flash memory logical page number ischecked to see if what is to be written is larger than the last flashmemory logical page that was written. If it is larger, the current writepage number is checked to see if it is equal to the last page writtenplus 1. If yes, the data from the host to the flash memory is programmedinto the buffer and the sector count number is decremented. Thisprogramming process is repeated until the sector count number is equalto “0”. If the current write page number is not equal to the last pagewritten plus 1, the data from the mother block (which is clean) is movedto the child block between the sections “last page written” and the“current write page”.

[0040] If what is to be written is not larger than the last flash memorylogical page that was written, the data from the mother block is movedto the child block between the sections “last page written” and the “endpage of this block”. Then, the mother block is erased. The link table inthe controller is updated substituting the original mother block addresswith the child block address. Then, the erased mother block is put backinto the FIFO queue as a clean block.

[0041] If what is to be written is larger than the last flash memorylogical page that was written, the data from the mother block is movedto the child block between the “last page written” and the “currentwrite page” sections. The data from the host to the flash memory isprogrammed into the buffer and the sector count number is decremented.The data is programmed until the sector count number equals zero.

[0042] For a read procedure of the flash memory device according to anembodiment of the present invention, the logical address from the USBhost is converted to the flash memory physical block and page address.Then, the current flash memory logical block is checked to see if whatis to be read is equal to the last flash memory logical block that wasread. If no, the data from the flash memory physical block and page isread and the sector count number is decremented. This process isrepeated until the sector count number equals “0”. If what is to be readis equal to the last flash memory logical block that was read, thecurrent flash memory logical page is checked to see if what is to beread is larger than the last flash memory logical page that was written.

[0043] If yes, the data from the flash memory physical block and page isread and the sector count number is decremented. This process isrepeated until the sector count number equals “0”. If what is to be readis not larger than the last flash memory page that was written, the datafrom the child block physical block and page is read and the sectorcount number is decremented. This process is repeated until the sectorcount equals “0”.

[0044] When the microprocessor begins to execute the command, the devicewill download its parameters from the host, for example, read or write,the vendor command packet. The system will judge the address mode by bit6 of the Device/Head byte. The flash memory device of the presentinvention supports both the logical block address (LBA) and the cylinderhead sector (CHS) mode. If the host provides the address using LBA mode,the device will convert it into CHS mode and then change the CHS modeinto the physical address.

[0045] When the device executes a read command, the controller willfirst read data from the flash memory, sector by sector to a buffer (512bytes) in the controller, then this sector will be sent to the host by aUSB engine. The whole command will be completed when the number ofsectors that have been sent to the host is equal to the sector count.

[0046] When the device executes a write command, the controller willread data from the host by the USB engine sector by sector to a buffer(512 bytes) in the controller, and then this sector will be stored inthe flash memory. The whole command will be completed when the number ofsectors that have been sent to the flash memory is equal to the sectorcount.

[0047] The device can support more than one piece of flash memory. Inthe present invention, multiple chip select pins are provided. When thedevice is initialized, it will check the type of the flash (thecapacity) being used on board and how many chips the system has and thedevice will add up all the memory chips to find out the total capacity.When the host needs this kind of data, the device will provide the totalcapacity to the host, not just the capacity of one chip.

[0048] When the host sends a certain address (logic) to the device, thedevice will perform a calculation to find the exact chip andcorresponding address that the host wants to access. Then the devicewill use the calculated address and enable the chip select pin.

[0049] It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary, andare intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention. In the drawings,

[0051]FIG. 1 is a diagram showing a layout of the universal serial busflash memory integrated circuit device according to an embodiment of thepresent invention.

[0052]FIG. 2 is a block diagram of a flash memory integrated circuitdevice controller according to an embodiment of the present invention.

[0053]FIG. 3 is a block diagram showing the system architecture of aflash memory integrated circuit device according to an embodiment of thepresent invention.

[0054]FIG. 4 is a flowchart showing the application of the USB protocolfor various operating systems according to an embodiment of the presentinvention.

[0055]FIG. 5 is a table listing parameters of the USB protocolimplemented in the flash memory device according to an embodiment of thepresent invention.

[0056]FIG. 6 is a flowchart showing the write procedure of the flashmemory device according to an embodiment of the present invention.

[0057]FIG. 7 is a flowchart showing the read procedure of the flashmemory device according to an embodiment of the present invention.

[0058]FIG. 8 is a block diagram showing writing data to a new blockaccording to an embodiment of the present invention.

[0059]FIG. 9 is a block diagram showing writing additional pages of dataaccording to an embodiment of the present invention.

[0060]FIG. 10 is a block diagram showing the mother and child techniqueaccording to an embodiment of the present invention.

[0061]FIG. 11 is a diagram showing the link table according to anembodiment of the present invention.

[0062]FIG. 12 is a diagram showing the head pointer and tail pointeroperation of an embodiment of the present invention.

[0063]FIG. 13 is a diagram showing the link table before programmingaccording to an embodiment of the present invention.

[0064]FIG. 14 is a diagram showing the head pointer and tail pointeroperation of an embodiment of the present invention.

[0065]FIG. 15 is a diagram showing a command packet structure accordingto an embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0066] Reference will now be made in detail to the preferred embodimentsof the present invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

[0067] Referring to FIG. 1, the universal serial bus flash memoryintegrated circuit device, referenced by 5, comprises a controller 40,at least one flash memory chip 50, a USB connector 10 adapted forconnecting the flash memory integrated circuit device 5 to an externalUSB host (not shown). The universal serial bus flash memory integratedcircuit device 5 further comprises an extension stack connector 20 thatallows for extending a number of flash memories 120. The extension stackconnector 20 connects flash memory (or flash memories) 120 to thecontroller 40. In this way, the memory capacity of the universal serialbus flash memory device 5 can be conveniently expanded as required.

[0068] The controller 40 is the major component of the device. Thecontroller 40 controls commands and data between the USB connector 10and the USB host and, manages data in the at least one flash memory chip50 and the connected flash memory or memories 120. It is preferred thatthe controller 40 is of a single chip design that does not need externalROM or RAM.

[0069] The universal serial bus flash memory integrated circuit device 5further comprises an I/O (input/output) control interface 30 for systeminput/output control.

[0070] Refer to FIG. 2, which is a block diagram of a flash memoryintegrated circuit device controller 200 according to the presentinvention.

[0071] The controller 200 provides a numerous functions. Among thesefunctions is controlling the USB interface 210.

[0072] The controller 200 is designed subject to the USB specificationfor physical and logical protocol. The controller 200 further comprisesa system buffer 250 or FIFO controller buffer.

[0073] The controller 200 receives command and parameter packets fromthe USB host, which are then stored in the system buffer 250 defined bythe controller 200. The controller 200 is also responsible forcontrolling the transfer of data to and from the USB host.

[0074] In addition, the controller 200 also provides status data to theUSB host.

[0075] When the host sends a write command, an interrupt is generatedand sent to the controller microprocessor, referenced by 220, to informthe microprocessor 220 of the command and the command location.

[0076] The microprocessor 220, for example an 8 or 16-bitmicroprocessor, is the major component of the controller 200. Themicroprocessor 220 reads the USB commands and parameters from the systembuffer 250, and also executes the commands with parameters.

[0077] The microprocessor 220 manages and maps the USB FIFO address tothe controller system buffer 250 while receiving or transferring data toand from the USB host.

[0078] Also, the microprocessor 220 manages commands such as erase,program, or read for the flash memory array. In addition, themicroprocessor 220 executes the addressing method according to thealgorithm of the controller 200.

[0079] Microprocessor ROM, referenced by 230, stores the program code ofthe controller 200, which is built in the controller 200. MicroprocessorRAM, referenced by 240, is a system RAM used by the controller 200 whenexecuting USB commands or the flash algorithm. By eliminating therequirement for off-chip memory, the system cost is reduced.

[0080] A system buffer 250 is used as a cache, which is provided forbuffering between the USB interface 210 and the flash memory arrayinterface, referenced by 260. It is also the FIFO of the USB protocoland the direction map to the buffer. The microprocessor 220 manages theaddresses of this buffer. As required, the buffer can be accessed bybyte or word.

[0081] The flash memory integrated circuit device of the presentinvention further comprises a hardware state machine for creating theread and write timing to the system buffer 250 between the USB host andthe flash memory.

[0082] The flash memory array interface 260 controls the read and writecommands to the flash memory array. According to the present invention,the flash memory array interface 260 is a pure hardware circuit.

[0083] An ECC circuit 270 encodes the ECC code while data is writingfrom the system buffer 250 to the flash memory array interface 260 anddecodes the ECC code while data is read from the flash memory arrayinterface 260 to the system buffer 250. If an ECC error occurs, the ECCcircuit 270 will determine the word or byte address in the buffer cacheand correct the error.

[0084] The I/O control interface. Referenced by 280, enables the systemto run other input/output controls.

[0085]FIG. 3 is a block diagram of the system architecture of a flashmemory integrated circuit device constructed according to the presentinvention.

[0086] Certain operating systems of the USB host 300 such as Windows MEand Windows 2000 contain default USB device drivers. Other operatingsystems may require the need for a USB device driver to be installed onthe host.

[0087] The USB command implementation, referenced by 320, receivescommands and from the USB host 300 and a parameter controller 305 via aUSB connector 310, stores received commands in a register defined by theparameter controller 305, and outputs an interrupt to inform themicroprocessor of the reception of a command.

[0088] The controller 305 receives and transfers data to and from theUSB host 300 subject to USB logical and physical specifications.

[0089] The addressing method, referenced by 330, is adapted to manageflash memory 340 erase, read, and write commands as well as physical tological mapping.

[0090]FIG. 4 is a flowchart of the application of the USB protocol forvarious operating systems. When the USB Host writes a command andparameter to the memory storage device in Step 410, the controller willstore it in a specified register and generates an interrupt to themicroprocessor in Step 420. The data will then be read by themicroprocessor as information from the USB host in Step 430.

[0091] In Step 440, the microprocessor begins execution of the commandaccording to the parameter. If the command is a write command, the datafrom the USB host to the buffer cache is received in Step 450.

[0092] The microprocessor then converts the logical address to the flashmemory physical address in Step 460. The microprocessor thenreads/writes data to/from flash memory in Step 470.

[0093] In Step 480, the data is transferred to the USB host if thecommand is a read command.

[0094] According to the standard USB specification, the requestparameter comprises 7 bits as shown in FIG. 5.

[0095] Bits D6-D5 of bmRequest Type designate the type of commandprotocol. The types include standard, class, and vendor. The flashmemory device of the present invention supports all three of these typesof protocols.

[0096] The standard type is the standard device request, which is acommon command such as USB_Get_Status or USB_set_Feature.

[0097] An embodiment of the flash memory integrated circuit device ofthe present invention utilizes the USB mass storage class with thebulk/control/interrupt transport.

[0098] Due to the physical limit of the Flash RAM, before the writecommand can be done, an erase command must be executed first. Typicalflash memory can function normally only until being erased about onemillion times, so minimizing the erase steps to maximize the flashmemory's usage life is very important. Therefore, the present inventionprovides a link table and a mother/child framework to achieve this aim.

[0099] Following is a description of the use of the link table. Wheninitializing flash, all blocks are searched and a record of therelationship between the physical and logical block that the search hasfound, becomes the link table. At the same time, the unused physicalblocks are put into the spare region for the FIFO queue to use.

[0100] Next, the logical block in the Link Table is used to find thecorresponding physical block address. By doing so, data associated witha particular physical block can accurately be written or retrieved.

[0101] Refer to FIG. 8, which is a block diagram showing writing data toa new block according to the present invention. When writing data to theflash memory, an erased block (new block) 810 may need to be taken toreplace an old block 800. Then, data is written into the new block 810.Finally, the unchanged data is moved from the old block 800 to the newblock 810. This completes the action of writing a page's data.

[0102] If multiple pages of data are to be written, the above steps arerepeated. Refer to FIG. 9, which is a block diagram showing writingadditional pages of data according to the present invention. Data iswritten into the new block 910 and the unchanged data is moved from theold block 900 to the new block 910.

[0103] However, if data is repeatedly written into the same block, manyunnecessary erase and move actions will be performed. This not onlywastes time but also reduces the lifetime of the flash.

[0104] Refer to FIG. 10, which is a block diagram showing the mother andchild technique according to an embodiment of the present invention.Therefore, in the flash memory device of the present invention, theerase action is avoided when repeatedly writing data to the same blockand the move action is performed only when changing blocks. All data iswritten into the new block (child block) 1010 first. Then, the unchangeddata is moved from the old block (mother block) 1000 into the new block1010. By using this method, not only is the lifetime of the flashincreased but the efficiency of the device is also increased.

[0105] Please refer to FIG. 11, which is a diagram showing the linktable according to an embodiment of the present invention. Following isa write data example. The link table links a physical block address 1100and a logical block address 1110. 32 sectors of data are to be writtento flash which starts at block/page 0/0. The total physicalblock/logical block is 1024/992. The total spare blocks for the FIFO is32. No blocks are defective. There are 32 pages per block.

[0106] Refer to FIG. 12, which is a diagram showing the head pointer andtail pointer operation of an embodiment of the present invention, FIG.13, which is a diagram showing the link table before programmingaccording to an embodiment of the present invention, and FIG. 14, whichshows the head pointer and tail pointer operation of an embodiment ofthe present invention. According to this example, child block 1300number 03E0h, which is pointed to by the head pointer 1210 is taken fromthe FIFO spare region 1200. The head pointer 1410 is then incrementedand 32 pages of data are programmed into the child block 1300.

[0107] Child block 1300 number 03E0h is filled into the mother block's1310 logical block address 0000h in the link table. Mother block 13100000h is erased and the tail pointer 1220 is incremented. Then, motherblock 1310 number 0000h is filled into the tail pointer 1420 pointaddress in the spare region.

[0108] Reference will now be made to a description of a write procedureaccording to an embodiment of the present invention.

[0109] The USB Host writes the corresponding write command and theaddress parameter to the memory storage device which then beginsexecution of the program flash algorithm.

[0110] Refer to FIG. 6, which is a flowchart showing the write procedureof the flash memory device according to an embodiment of the presentinvention.

[0111] First in Step 601, the logical address from the USB host isconverted into flash memory physical block and page address.

[0112] Then in Step 602, the controller checks to see if a child blockexists. If no child block exists, proceed to Step 605. If a child blockexists, in Step 603, the current flash memory's logical block is checkedto see if what is to be written is equal to the last flash memorylogical block that was written. If it is not equal, proceed to Step 611.

[0113] If it is equal, in Step 604, the current flash memory logicalpage number is checked to see if what is to be written is larger thanthe last flash memory logical page that was written. If yes, proceed toStep 610, otherwise go to Step 611.

[0114] In Step 605, a clean block is taken from the FIFO queue to createa child block for the current write command.

[0115] In Step 606, the current flash memory logical page number ischecked to see if what is to be written is equal to “0” or not. If equalto “0”, proceed to Step 608.

[0116] If not equal to “0”, in Step 607, the data from the mother blockis moved to the child block between the “last page written” and the“current write page” sections.

[0117] In Step 608, the data from the host to the flash memory isprogrammed into the buffer and the sector count number is decremented.

[0118] In Step 609, if the sector count number is equal to “0”, go to“End”, otherwise go to Step 608.

[0119] In Step 610, if the current write page number is equal to thelast write page number plus 1, go to Step 608, otherwise go to Step 607.

[0120] In Step 611, the data from the mother block is moved to the childblock between the sections “last page written” and the “end page of thisblock”, the mother block is erased, the link table in the controller isupdated substituting the original mother block address with the childblock address, and the erased mother block is put back into the FIFOqueue as a clean block.

[0121] Refer to FIG. 7, which is a flowchart showing the read procedureof the flash memory device according to an embodiment of the presentinvention.

[0122] In Step 701, the Logical Address from the USB host is convertedto the flash memory physical block and page address.

[0123] In Step 702, the current flash memory logical block is checked tosee if what is to be read is equal to the last flash memory logicalblock that was read. If yes, proceed to the Step 705, otherwise go toStep 703.

[0124] In Step 703, the data from the flash memory physical block andpage is read and the sector count number is decremented.

[0125] In Step 704, the sector count number is checked to see if it isequal to “0”. If equal to “0” go to “End”, otherwise return to Step 703.

[0126] In Step 705, the current flash memory logical page is checked tosee if what is to be read is larger than the last flash memory logicalpage that was written. If yes, proceed to the Step 703, otherwise go toStep 706.

[0127] In Step 706, the data from the child block physical block andpage is read and the sector count number is decremented.

[0128] In Step 707, the sector count number is checked to see if it isequal to “0”. If yes, then go to “END”, otherwise go to Step 705.

[0129] Refer to FIG. 15, which shows a command packet according to anembodiment of the present invention. When the microprocessor begins toexecute the command, the device will download its parameters from thehost, for example, read or write, the vendor command packet is as shownin FIG. 15.

[0130] The system will judge the address mode by the Device/Head byte.The flash memory device of the present invention supports both the LBAand CHS mode.

[0131] If the host provides the address using LBA mode, the device willconvert it into CHS mode and then change the CHS mode into the physicaladdress.

[0132] When the device executes a read command, the controller willfirst read data from the flash memory, sector by sector to a buffer (512bytes) in the controller, then this sector will be sent to the host by aUSB engine. The whole command will be completed when the number ofsectors that have been sent to the host is equal to the sector count.

[0133] When the device executes a write command, the controller willread data from the host by the USB engine sector by sector to a buffer(512 bytes) in the controller, and then this sector will be stored inthe flash memory. The whole command will be completed when the number ofsectors that have been sent to the flash memory is equal to the sectorcount.

[0134] The device can support more than one piece of flash memory.According to the present invention, multiple chip select pins areprovided. When the device is initialized, it will check the type of theflash (the capacity) being used on board and how many chips the systemhas and the device will add up all the memory chips to find out thetotal capacity. When the host needs this kind of data, the device willprovide the total capacity to the host, not just the capacity of onechip.

[0135] When the host sends a certain address (logic) to the device, thedevice will perform a calculation to find the exact chip andcorresponding address that the host wants to access. Then the calculatedaddress is used and the chip select pin is enabled.

[0136] Furthermore, the flash memory chip and controller as mentioned inthe aforesaid description are of single chip design to minimize thedimensions of the universal serial bus flash memory integrated circuitdevice without the need of external RAM or ROM.

[0137] It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

What is claimed is:
 1. A universal serial bus flash memory integratedcircuit device formed of an integrated circuit package containing acontroller and at least one flash memory chip for controlling commandsand data between said at least one flash memory chip and a hostcomputer, the universal serial bus flash memory integrated circuitdevice comprising: a universal serial bus (USB) connector for connectingthe universal serial bus flash memory integrated circuit device to ahost computer; an extension stack connector that allows for extending anumber of flash memories; and an I/O (input/output) control interfacefor system input/output control.
 2. The universal serial bus flashmemory integrated circuit device of claim 1, further comprising a systembuffer for buffering between said host computer and said at least oneflash memory chip.
 3. The flash memory device of claim 2, furthercomprising a hardware state machine for creating the read and writetiming to the system buffer.
 4. The flash memory device of claim 1,further comprising an error correction code (ECC) circuit for encodingan ECC when data is written to said at least one flash memory chip andfor decoding the ECC when data is read from said at least one flashmemory chip.
 5. The flash memory device of claim 4, wherein said errorcorrection code (ECC) circuit further comprises determining an addressof invalid data when an error occurs and correcting the error.
 6. Theflash memory device of claim 1, further comprising a flash memoryinterface for controlling read and write commands to external flashmemories connected to said extension stack connector.
 7. The flashmemory device of claim 1, wherein said at least one flash memory chipand said controller are of a single chip design.
 8. The flash memorydevice of claim 1, further comprising a microprocessor for executingcommands with parameters from the host computer.
 9. The flash memorydevice of claim 8, wherein said controller comprises: a microprocessoradapted to execute commands with parameters from the host computer; asystem buffer for buffering between said at least one flash memory chipand the host computer; and a hardware state for creating the read andwrite timing to the system buffer.
 10. The controller of the flashmemory device of claim 1, wherein said controller is of a single chipdesign that does not need external random access memory (RAM) or readonly memory (ROM).
 11. A universal serial bus flash memory integratedcircuit device comprising: a universal serial bus for connecting theflash memory device to a host computer; at least one flash memory modulefor storing data; a flash memory interface for controlling read andwrite commands sending to said at least one flash memory module; a flashmemory extension interface for enabling the universal serial bus flashmemory integrated circuit device to be electrically connected toexternal flash memories; a universal serial bus interface forcommunication between said at least one flash memory module and the hostcomputer; and a controller for controlling commands and data between thehost computer and the universal serial bus flash memory integratedcircuit device and for managing data in the at least one flash memorymodule, said controller comprising: a system buffer for bufferingbetween the host computer and the flash memory device; a microprocessorfor executing commands with parameters from the host; and a statemachine for creating read and write timing to the system buffer.
 12. Theuniversal serial bus flash memory integrated circuit device of claim 11,wherein said controller controls transmission of data to and from thehost computer.
 13. The universal serial bus flash memory integratedcircuit device of claim 11, wherein said controller controls saiduniversal serial bus interface.
 14. The universal serial bus flashmemory integrated circuit device of claim 11, wherein said controllerreceives commands from the host computer.
 15. The universal serial busflash memory integrated circuit device of claim 11, wherein saidcontroller provides a status to the host computer.
 16. The universalserial bus flash memory integrated circuit device of claim 11, whereinsaid microprocessor reads commands and parameters from said systembuffer.
 17. The universal serial bus flash memory integrated circuitdevice of claim 11, wherein said microprocessor executes commands withparameters from the host computer.
 18. The universal serial bus flashmemory integrated circuit device of claim 11, wherein saidmicroprocessor manages and maps universal serial bus address to saidsystem buffer while receiving or transferring data to and from the hostcomputer.
 19. The universal serial bus flash memory integrated circuitdevice of claim 11, wherein said microprocessor manages commands oferase, program, and read for said at least one flash memory module. 20.The universal serial bus flash memory integrated circuit device of claim11, wherein said microprocessor executes addressing methods subject toan algorithm of said controller.
 21. The universal serial bus flashmemory integrated circuit device of claim 11, wherein saidmicroprocessor manages system buffer addresses.
 22. The universal serialbus flash memory integrated circuit device of claim 11, wherein saidmicroprocessor further comprises: a ROM for storing program code of saidcontroller; and a RAM for use by said controller when executingcommands.
 23. The universal serial bus flash memory integrated circuitdevice of claim 11, further comprising an extended memory boardconnected to said flash memory extension interface for extending memoryfor the universal serial bus flash memory integrated circuit device.